1. Field of the Invention
The present invention relates to an output circuit in a semiconductor integrated circuit, more particularly to an output circuit with reduced power consumption.
2. Description of the Related Art
Conventional output circuits are generally structured as shown in FIG. 1, comprising a buffer B1 that receives an input signal S1 and drives two output transistors P3, N3. As shown in FIG. 2, the input signal S1, the signal SG1 applied to the gate electrodes of the output transistors P3, N3, and the output signal (OUT) all swing between the same power supply potential (VCC) and ground potential (GND). Since the output transistors are normally designed with large gate widths to provide adequate driving capability, the amount of current consumed in charging and discharging the capacitance of their gates is not negligible, particularly in a high-voltage output circuit.
Japanese Patent Application Publication No. 2000-49584 describes a high-voltage output circuit with a pair of level shifters that convert a narrow-swing input logic signal to two gate-driving signals, one with a raised high logic level, the other with a lowered low logic level. This scheme reduces the gate voltage swings, but the voltage shifters have fixed output ranges that overlap and cannot be adjusted.